1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of inserting decoupling capacitors in an integrated circuit design.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells.
An IC chip is fabricated by first conceiving a logical (behavioral) description for the circuit, and converting that logical description into a physical description, or geometric layout. This process is carried out in steps, such as first generating a register-transfer level (RTL) description of the circuit based on the logical description, and then using logic synthesis to derive a gate level description or “netlist.” A netlist is a record of all of the nets (interconnections) between cell pins, including information about the various components such as transistors, resistors and capacitors. The circuit layout is then checked to insure that it meets all of the design requirements, particularly timing requirements, and may go through several iterations of analysis and refinement.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located in a layer of an integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices such as microprocessors and application-specific integrated circuits (ASICs), physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different hardware description programming languages (HDL) have been created for electronic design automation, including Verilog, C, VHDL and TDML. A typical electronic design automation system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
One problem that has arisen in these modern electronic devices relates to noise in the power grid of the device. Substantial noise is generated in an integrated circuit chip as digital electronic functions are interconnected or decoupled. The power grid provides the power and ground signals throughout the chip, and these are among the most important signals to control reliably, since supply voltage variations can lead not only to problems related to spurious transitions in some cases (particularly when dynamic logic is used), but also to delay variations and timing unpredictability. Even if a reliable supply is provided at an input pin of a chip, it can deteriorate significantly within the chip due to imperfections in the conductors that transmit these signals throughout the chip.
Noise in modern electronic circuits is particularly troublesome as it increases the requirements on the noise margins and other circuit parameters. Noise margins have been greatly reduced in modern designs due to the lowering of supply voltages and the presence of a larger number of potential noise generators. With technology scaling, the trend for high performance integrated circuits is toward every higher operating frequencies, lower supply voltages, and higher power dissipation. These features cause a dramatic increase in the currents being delivered through the on-chip power grid.
One solution to this problem lies in the use of decoupling capacitors. On-chip decoupling capacitors (dcaps) attached to the power grid can reduce power supply induced noise. For example, in a CMOS reduced instruction set computing (RISC) microprocessor design, as much as 160 nF of on-chip decoupling capacitance may be added to control power supply noise. In another example, the on-chip decoupling capacitance may be sized at ten times that of the total active circuit switching capacitance. The closer decoupling capacitors can be placed in relation to the noise source (such as a switching transistor), the more effective the decoupling will be, primarily due to a decreased inductance in series with the decoupling capacitance. Decoupling capacitors may be provided underneath devices at the surface of an integrated circuit, or distributed in a carrier of the chip. Decoupling capacitors also provide a key benefit of power savings by removing the superimposed signal from the power rail.
Dcaps are generally evenly placed based on some percentage set by the design team along a fixed grid, as illustrated in FIG. 1 for an exemplary layout 1 of circuit elements or cells 2. Two parallel power rails 3 are provided along either side of layout 1, and dcaps 4 are placed at regular intervals along power rails 3. The problem with this approach is that the resulting dcap placement is not necessarily ideal based on the locations of the logic gates, and can negatively impact overall placement results such as timing.
In a traditional synthesis environment as exemplified by FIG. 2, dcap insertion has typically been a pre-placement procedure. The design process begins with the dcap grid placement 5. After dcap grid placement, design synthesis 6 and design placement 7 are carried out. Synthesis and design may be integrated in placement-directed synthesis to overcome problems in achieving timing closure, including for example technology mapping, physical placement, electrical correction, and timing legalization. The process ends with design routing (wiring) to properly connect the placed components while obeying all design rules for the integrated circuit 8. It is impossible to optimize dcap placement in this process since the dcaps are all inserted prior to placement of the circuit elements in the geometric layout.
As an alternative to the methodology of FIG. 2, dcaps may be inserted once the design process is substantially complete (including synthesis, placement, and physical design). Existing tools can highlight areas or nets that appear to be particularly sensitive to coupling or which may create coupling problems. Dcaps can then be inserted at those areas, but this ad hoc approach severely limits placement to available locations. This approach is also manually intensive.
In light of the foregoing, it would be desirable to devise a more flexible method of dcap placement which could take the logic layout into consideration. It would be further advantageous if the method could integrate dcap insertion into the full automated flow for physical synthesis to achieve improved timing results.